1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device including a step-down circuit for stepping down a power supply voltage externally applied and applying the voltage to an internal signal processing circuit as an internal power supply voltage.
2. Description of the Prior Art
With the progress of the manufacturing process of a semiconductor integrated circuit or finer circuit elements, from the viewpoint of reliability, a technique is generally used in which a step-down circuit is internally provided to step down an external power supply voltage of, e.g., 5 V to a voltage of 3 to 4 V, and the voltage is applied to an internal signal processing circuit. However, voltage acceleration cannot be performed with such a stepped-down power supply voltage for a burn-in test or an aging test. For this reason a life test cannot be efficiently performed.
As an example of a means of solving this problem, Japanese Unexamined Patent Publications Nos. 64-81019, 3-149876, and 3-160699 disclose a technique in which an exclusive external terminal is provided, and a control signal is externally supplied to this terminal, thereby controlling the presence/absence of a voltage drop operation or the value of a voltage drop.
FIG. 1 is a circuit diagram of a semiconductor integrated circuit found in Japanese Unexamined Patent Publication No. 64-81019. Referring to FIG. 1, in this semiconductor integrated circuit, when a high operating power supply voltage is required for burn-in test or voltage acceleration test, a ground potential is applied to an external control terminal PC which is exclusively used for control. Transistors Q2 and Q3 in the step-down circuit control circuit are turned off, and a transistor Q1 is turned on. With this operation, the voltage at an internal power supply terminal Vddi is almost equalized with the voltage at an external power supply terminal Vddo. A voltage higher than the power supply voltage (3 to 4 V) in a normal operative state is obtained to perform voltage acceleration.
Also in the semiconductor integrated circuit device in Japanese Unexamined Patent Publication No. 3-149876, as shown in FIG. 2, a control signal C is input to an internal step-down power supply circuit from an external terminal which is exclusively used for control, thereby controlling the presence/absence of the voltage drop operation. Referring to FIG. 2, a reference voltage VR applied to the gate electrode of a transistor Q4 defines an output level VCL from an internal step-down power supply circuit. When voltage acceleration is to be performed, a ground potential is applied to the control signal C to turn off a transistor Q6, thereby setting the output VCL in a high impedance state in accordance with the OFF state of the transistors Q4, Q1, and Q3. At this time, when a power supply voltage VCCE is applied from another external power supply voltage line, voltage acceleration can be performed.
In the semiconductor integrated circuit device disclosed in Japanese Unexamined Patent Publication No. 3-160699, a test mode is set in accordance with an internally generated control signal without using any external terminal exclusively used for control. As shown in FIG. 3, the step-down circuit .of this integrated circuit device is constituted by a reference voltage generation circuit VrG, a switch circuit SC, and a step-down circuit VD. Referring to FIG. 3, during the normal operation, a control signal Te is set to "L" level. A transistor Q14 is turned on to transmit a reference voltage Vr1 generated by the reference voltage generation circuit VrG to the step-down circuit VD, thereby equalizing an internal power supply voltage Vcd with the reference voltage Vr1. In the test mode, the control signal Te is set to "H" level. A transistor Q15 is turned on to transmit a reference potential Vr2 (=external power supply voltage VCC) to the step-down circuit VD. The output voltage Vcd from the step-down circuit VD is almost equalized with the external power supply voltage VCC, so voltage acceleration can be performed.
If the step-down circuit having the above arrangement is applied to, e.g., a dynamic RAM, the control signal Te in FIG. 3 is generated in a timing generation circuit (not shown) for generating various timing signals in combination with a row address strobe signal, a column address strobe signal, and a write enable signal, all of which are externally supplied to the RAM as starting control signals. Therefore, an external control terminal for setting a test mode, i.e, controlling the presence/absence of the voltage drop operation is not particularly needed. When the reference potential Vr2 for setting the output voltage from the step-down circuit VD to the power supply voltage Vcc upon voltage acceleration is externally applied through an address input terminal A0, the output voltage from the step-down circuit in the test mode can be arbitrarily set.
In the semiconductor integrated circuit incorporating a step-down circuit as disclosed in Japanese Unexamined Patent Publications Nos. 64-81019 or 3-149876, when a conventional method is used in which the operative/inoperative state of the internal step-down circuit is controlled using an external terminal exclusively used for control, an external terminal and a pad, which are exclusively used for this purpose, are needed. As a result, an exclusive pin is needed to mount this integrated circuit on a package, and the size of the package is increased. In addition, the space for mounting the integrated circuit on a board is accordingly increased.
According to the invention disclosed in Japanese Unexamined Patent Publication No. 3-160699, setting of the test mode or the test voltage value can be controlled without adding an external terminal. In this case, however, to set the test mode, the starting control signals for the integrated circuit must be combined and fixed for the test mode. In addition, the input level to at least one external terminal must be fixed to a test voltage. Therefore, voltage acceleration in the operative state (e.g., dynamic operation of a dynamic RAM) of the integrated circuit cannot be performed.